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Zhuzhou Shifeng power semiconductors

Shifeng power semiconductors include thyristors, IGBTs and silicon-carbide devices. Their voltage, current, switching-frequency and thermal duties differ, so chip data must be qualified together with packaging, gate drive and the application system.

Formation and regional foundations

Traction and high-voltage transmission demand drove large-power device development, with materials, wafers, packaging tests and converter applications repeatedly calibrating one another in Zhuzhou. Wide-bandgap devices expand frequency and temperature windows while raising new gate-oxide, parasitic and customer-qualification challenges.

Power semiconductors control large current in traction, grids and new-energy systems rather than information bits. Shifeng brings materials, chips, packaging and applications together, while thyristors, IGBTs and silicon-carbide devices retain different structures and operating windows. Package thermal resistance, drive and system protection often decide success before one headline parameter.

Core geography: A Tianxin-area chain in Shifeng District combining substrates and process materials, chip fabrication, advanced packaging, power-module testing and rail power-electronics applications

Power travels from wafer through package to traction motor

How six interfaces jointly control switching loss and junction temperature

The structure follows technical responsibility. Chip fabrication, packaging and system integration may belong to separate entities, and arrows show qualification dependence rather than designated procurement.

  • Silicon and SiC materials — Crystal defects and wafer condition enter the device start.
  • Chip fabrication — Doping, etching and metallisation create the switch.
  • Interconnect and power package — Joints, bonds and substrate carry current and heat.
  • Electrical and life test — Static, dynamic and cycling tests screen devices.
  • Drive, busbar and cooling — Peripheral circuits set actual waveform and junction temperature.
  • Traction and grid systems — Load profiles and faults complete final judgement.

01 · Thyristors carry high power without chasing high-frequency turn-off

Device structure must fit grid and traction commutation.

A thyristor can carry very large current and blocking voltage after triggering, while traditional devices turn off through current zero or external commutation. It suits high-voltage direct current, industrial rectification and some traction duties but is not the answer to every fast-switching problem. Zhuzhou’s large-power heritage grew from these systems, so surge, conduction loss and commutation come first.

Selecting a thyristor by rated voltage alone can miss repetitive peaks, current rise and voltage sharing in series or parallel. Enlarging die area to reduce conduction loss adds capacitance, cost and mechanical stress. If the system cannot provide reliable commutation, a robust device still cannot turn off. The thyristor belongs with valve structure, cooling and protection rather than as an isolated high-current switch. In a series valve, variation in grading resistors, capacitors and cooling contact can drive voltage toward one thyristor, so equal ratings still require hot-state observation of continuing distribution drift.

Application review lists normal current, overload, short circuit and commutation-failure waveforms and translates allowable junction temperature to coolant inlet and ambient. A prototype valve measures current sharing, voltage sharing and heat distribution before repeated surge and protection tests. Device lot, clamping force and thermal interface remain recorded so a failure can be assigned to chip, assembly or control.

  • Thyristor selection begins with commutation, surge and cooling together

02 · IGBT brings gate control into medium- and high-power switching

Conduction, switching and short-circuit withstand require balance.

An IGBT uses an insulated gate to control large current in traction converters, industrial drives and new-energy equipment. Chip structure simultaneously shapes on-state voltage, switching tail current and short-circuit withstand, so no grade optimises every measure. Shifeng proximity lets chip design receive real converter waveforms, yet each programme still selects around switching frequency and load profile.

Chasing lower on-state voltage can increase turn-off loss, while faster switching raises interference and overvoltage. Data-sheet conditions differ from a customer bus, inductance and gate resistance, so adding published switching energies can miss reality. Parallel dies also face temperature coefficient and dynamic sharing; acceptable module-average current does not give every die equal thermal margin. Gate-loop inductance and emitter connection between chips alter switching sequence, while total current at module terminals cannot reveal the brief excess carried by one parallel unit.

Build a double-pulse test with the target busbar, capacitor and gate drive, stepping gate resistance while recording overshoot, loss and ringing, then compare die temperature within the module. Short-circuit testing joins protection delay instead of proving only a nominal withstand time. Final parameters enter the system thermal model and face a long load cycle comparing calculation with measurement.

  • IGBTs must be measured in the target bus, drive and protection

03 · Silicon carbide expands high-temperature frequency while magnifying parasitics

Material advantages appear only after package and drive cooperate.

Silicon carbide offers higher critical field and faster switching, handling high voltage with smaller die area and potentially lower switching loss. It is also more sensitive to crystal defects, gate-oxide reliability and high-frequency parasitics, where small package or drive changes can cause ringing. Shifeng is developing a silicon-carbide device route, but maturity still belongs to the particular device, package and application.

Replacing a silicon IGBT while retaining the old busbar, drive and filter can turn SiC speed into overshoot and electromagnetic interference. Slowing the gate heavily to suppress ringing gives away efficiency. A higher allowable junction temperature also does not relax cooling because joints, substrates and nearby capacitors have lower limits. Only system-level optimisation determines the realised benefit. A higher voltage slew rate can send common-mode current through parasitic capacitance into motor bearings, sensors or control ground, making an efficiency gain worthless if the system misbehaves.

A new device first establishes a safe window with adjustable drive and a low-parasitic fixture before the real bus and load are introduced. Tests cover negative gate bias, Miller effect, short circuit, avalanche or surge and high-temperature leakage, with package hot spots checked by imaging or structural estimates. System efficiency, volume and filter changes remain together rather than reporting die-loss reduction alone. Probe bandwidth, ground lead and measurement point first face a known pulse; otherwise fixture ringing may be mistaken for device overvoltage and produce an unnecessarily narrow safe window.

  • SiC value requires system efficiency, volume and reliability together

04 · Wafer yield comes from stability across hundreds of steps

Material defects, cleanliness and process windows converge at the end.

Power-chip fabrication passes through epitaxy, lithography, implantation or diffusion, etching, dielectrics and metallisation. Particles can cause shorts or leakage, while doping and thickness shifts alter breakdown and conduction, often appearing only at wafer probe. Shifeng includes materials and equipment, but a stable line still depends on continuous process, tool and metrology control at every step.

Final yield alone cannot show whether defects came from wafer material, a tool or design edge, and a short-term rise may reflect changed screening. Changing several lots and steps together for output removes controls and slows learning. Improvement needs spatial defect distribution, parameter drift and tool history so each adjustment points to a plausible mechanism.

Link incoming wafers, critical films, lithography defects and electrical parameters, clustering anomalies by wafer position and tool chamber. A process change uses a control lot with observation measures and failure disposition defined before scale-up. After major maintenance, monitor wafers restore the baseline, and product resumes only when metrology and electrical behaviour both return to window.

  • Process changes need control lots and spatial defect information

05 · Power packaging carries current, insulation, heat and mechanical load

Joints and bonds often reveal weakness during cycling.

A power module mounts several dies on insulated substrates and baseplates, using solder, sinter or bonds for high-current connections. Materials expand differently, so repeated heating and cooling shear joints, wires and interfaces. YueMo adds wafer-level and system packaging routes, while a particular power module still faces high-voltage insulation and thermal cycling. Voids, metal-layer thickness and insulation spacing in the package cross-section jointly alter heat flow, current distribution and local electric field.

A module with low initial thermal resistance can deteriorate as voids grow during cycling, while a bond that passes static pull may fatigue at current crowding. Average junction temperature misses edge dies and local joint hot spots. Package reliability cannot be inferred from a bill of materials; it combines structure, manufacturing distribution and temperature swing from the target load. A progressively slower thermal transient during power cycling can expose growth in a solder or sintered interface before final thermal resistance fails, so monitoring intervals must reveal that evolution.

Package trials record die position, joint thickness, voids and bonding settings, while electrothermal tests establish a baseline for each die. Power cycling follows target current and temperature swing with periodic thermal-resistance and voltage measurements, followed by cross-section and interface analysis. A changed substrate, solder or sinter cycle repeats high-voltage, thermal and mechanical qualification rather than only initial parameters.

  • Package life must be measured through target temperature swing and interface degradation

06 · Electrical testing must cover static, dynamic and abnormal states

One switching result cannot describe a device boundary.

Power devices commonly leave production after blocking, leakage, conduction and gate static tests, while application development also needs switching energy, reverse recovery, short-circuit and thermal data. Fixture inductance, current sensing and temperature can change dynamic results markedly. The Shifeng chain extends from chips into applications, making the test interface critical to meaningful parameter exchange. One switching trace must retain bus voltage, estimated junction temperature and gate conditions or it cannot support a system comparison.

Treating a laboratory typical value as guaranteed ignores lot distribution and worst conditions. Raising screening voltage indiscriminately can add stress without finding dynamic defects. Too many tests add cost and time, while too few transfer risk to an expensive system. A sound plan separates screening, sampling and type tests according to failure consequence and process variation.

Both sides first align waveform definitions, reference points, temperature and fixture parasitics, then exchange raw traces rather than summary values alone. Production screening targets quickly detectable defects, dynamic and life work uses lot sampling, and the application reproduces critical switching states. When results disagree, the same devices and calibration pieces travel between sites before product causes are debated. A stable reference device measured periodically across fixtures can separate product drift from probe or calibration drift and prevent both sides from arguing from different baselines.

  • Dynamic parameters must carry fixture, temperature and waveform definition

07 · Traction and grid load profiles decide device life

Routes, lines and faults keep junction temperature changing.

Rail traction cycles among acceleration, coasting and regenerative braking, while grid equipment may run steadily before a fault current arrives. Device life follows current, junction temperature and temperature swing over time, not hours at one rated point. Times Electric brings local devices into systems, allowing field load to calibrate chip and package test profiles back.

A continuous worst-point test can overstate a rare stress while missing fatigue from many smaller thermal swings. Designing around average load understates hills, congestion or weak-grid hot periods. Protection action also changes fault energy. A life model needs actual duty statistics and a clear division between events limited by control and those borne by the device.

Extract representative current, ambient and cooling data from vehicles or grid equipment, convert it into junction-temperature cycles and group by amplitude and count. Bench acceleration covers dominant damage mechanisms, followed by equipment routes confirming control, cooling and protection assumptions. Field anomalies retain pre- and post-fault waveforms and software revision, distinguishing rare events from sustained duty when life profiles change.

  • Device life tests should be driven by real load profiles rather than one rated point

08 · Production line, engineering lot and customer approval are different milestones

A technical direction becomes supply only through repeatable delivery.

A power-semiconductor programme moves through research samples, process definition, engineering lots, reliability and customer-system approval. Installed equipment establishes manufacturing capability, and a passing first wafer or lot shows the route can operate; neither proves sustained yield or delivery. Shifeng spans materials, chips, packaging and applications, while purchasing still asks the stage of the specific device. When a customer changes cold plate, driver revision or busbar around the same part number, the approved system boundary has changed and supplemental testing follows the affected loads.

Turning planned scale into current supply ignores ramp defects, material qualification and customer validation, while excluding every new project can miss a stable grade. Maturity is not one company label but a combination of die revision, package and application. A module approved in traction does not automatically receive equal approval in storage or automotive use.

Engagement lists device type, wafer and package revision, completed tests, remaining gates and deliverable volume without requiring sensitive yield disclosure. Initial application uses a traceable small quantity and returns switching, thermal and fault events. Manufacturing, critical-material or layout changes receive tests according to impact so commercial scale follows technical evidence rather than a promotional timetable. The first customer installation crosses cold start, rated load and protection events, with returned waveforms tied to individual device serial numbers.

  • Maturity belongs to a specific device revision, package and application

Sources and reading notes

Device comparison uses blocking voltage, operating current, switching frequency, junction temperature, surge or short-circuit duty and life profile. Bare die, discrete device, module and converter are distinct levels, as are laboratory sample, engineering lot and customer approval. A new line becomes supply only after stable process and application qualification.

  • Shifeng power semiconductors entered the 2025 national distinctive-cluster list.
  • Provincial material describes a chain from materials and equipment to chips, devices and applications.
  • The local industry spans thyristor, IGBT and silicon-carbide directions.
  • YueMo publishes wafer-level and system-in-package capabilities.

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Sources

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