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INDUSTRY CLUSTER · Electronics

Ganzhou Zhanggong printed circuit boards

Zhanggong PCB quality is formed before final electrical test. Copper-foil roughness, laminate dielectric properties, lamination flow, drill position, hole copper and solder-mask cleanliness jointly decide assembly. Ordinary multilayer, HDI and high-frequency boards use different structures, and customer data must remain aligned with manufacturing revision.

Formation and regional foundations

Zhanggong links copper foil, laminate and PCB, with Shenlian, Yihao and Chaoyue occupying different points in board manufacturing, foil or compliant recovery. Local plans also require testing and lawful recycling; foil capacity, projects under construction and terminal electronics do not become current PCB capability.

A customer sees a solder-masked board, while reliability hides in resin flow, layer registration, hole-wall copper and cleanliness. One wrong panel file, drill programme or image can distribute defects across the panel and leave them undiscovered until assembly or thermal cycling.

Core geography: An electronic-circuit manufacturing area in Zhanggong High-tech Zone linking copper foil, laminates, printed circuit boards, dedicated materials, testing and compliant recovery

Zhanggong PCB material and data handovers

On which panel a defect first appears

Material lots and customer data meet at panel identity; coupon, microsection and electrical test retain common coordinates.

  • Foil and laminate lots — Foil treatment side, laminate resin and lot dielectric data define the material starting point of the stack-up.
  • Stack-up and lamination recipe — Cores, prepreg, copper distribution and press cycle establish actual dielectric thickness and layer registration here.
  • Drilling and microvia programme — Drill revision, tool life, stack height and microvia energy determine hole location and wall condition.
  • Metallisation and plating baths — Desmear, activation, electroless copper and plating build the hole conductor, with the deepest holes as critical observations.
  • Imaging and solder mask — Outer imaging, solder-mask openings and final finish turn the network into a solderable pad interface.
  • Coupons and finished-board test — Impedance coupons, section coordinates and electrical test retain edge and network location instead of detaching averages from the board.

01 · Foil roughness affects both adhesion and high-frequency loss

A rougher upstream surface is not always safer.

A PCB stack begins with copper foil and laminate, whose thickness, surface profile and resin system determine both bond and signal loss. A rough surface can improve mechanical grip while lengthening the high-frequency current path. Dielectric constant, dielectric thickness and foil roughness therefore enter impedance and insertion-loss design together, and experience from ordinary digital boards does not establish fitness for high-frequency networks. Glass-weave openings can also place the two conductors of one differential pair over different dielectric regions, so stack-up review includes both weave and routing direction.

Material substitution is easily underestimated when grade names are similar. A change in resin cure, treated foil surface or lot dielectric data can move impedance, peel strength and high-frequency loss in different directions after lamination. If incoming inspection checks only labels and retains no representative coupon, later faults cannot be separated from etching or pressing effects. One average dielectric figure also hides panel and lot variation. Once prepreg exceeds its permitted exposure, normal appearance does not guarantee flow or fill; issued remnants therefore cannot return to mixed stock without a defined disposition.

Process preparation locks foil side, laminate grade and prepreg lot to the final stack, with incoming coupons retained through finished-board verification. Sections and electrical tests on the first pressed lot confirm copper, dielectric and bond condition and return results to material identity. A change in foil profile, resin system or supply lot requires renewed impedance and loss checks even when nominal thickness is unchanged. In a mixed lamination, low-flow and conventional prepreg locations are marked layer by layer so that a loading error cannot alter fill around a cavity edge.

  • Roughness and dielectric data enter stack selection.

02 · Inner-layer offset becomes permanent after lamination

Imaging, etching and treatment finish before lay-up.

Inner-layer circuitry becomes permanently enclosed after imaging, development and etching, making a wrong revision or scale error difficult to recover. Trace geometry, residual copper, core stability and bonding treatment all influence later registration, so targets must follow each core rather than exist only in panel data. Heavy copper and fine lines face different undercut and cannot share one empirical compensation. The first inner layer is measured in dense traces, isolated conductors and the edge of a copper field, since those locations respond differently to exposure and etching variation.

Without a checksum tied to core identity, an obsolete image can remain on the imager and place complete-looking networks in the wrong position. Excess etch compensation narrows fine lines, while moisture or thermal history changes core dimensions. After lamination, the symptom may appear as drill offset although the cause is earlier inner-layer scaling; targets, line geometry and revision must agree before lay-up. An inner layer with embedded resistance, capacitance or local heavy copper also receives a dedicated functional check rather than disappearing inside ordinary image rules; its readings identify component position and test direction instead of substituting a whole-panel average for a local network, and remain available for the corresponding post-lamination check.

The first image is scanned and compared with the final data checksum, layer number and core identity, followed by trace and target measurements. Residual copper and bonding treatment are inspected after etching; a faulty inner layer is not rescued by later drill compensation. Changes in data, material or copper weight require new scaling and etch allowance so every core has an unambiguous revision before lamination.

  • Registration targets follow every core.

03 · The lamination window decides whether resin fills every gap

Temperature, pressure and vacuum follow resin reaction.

Multilayer lamination must fill, cure and register the stack within the resin reaction window. Heating rate, vacuum, pressure, copper distribution and lay-up direction govern flow; too little resin leaves voids, while excessive flow thins the dielectric. A press curve is only a machine history and needs confirmation from finished thickness, sectioned dielectric, layer shift and glass-transition condition.

Uneven copper distribution can create resin-rich and resin-starved areas in the same panel while average thickness remains acceptable. A changed material lot may make an old press recipe produce local voids, and layer shift later appears as deficient annular ring during drilling. One edge section can therefore miss filling and registration problems near the panel centre.

Representative panels use the actual copper distribution. Thermocouples and press data capture heating, pressure and vacuum stages, followed by sections from different areas for dielectric, void and registration inspection. An anomaly changes the material combination or cycle rather than being hidden by later copper. A new prepreg lot, copper balance or stack requires renewed recipe confirmation so impedance and reliability rest on the physical structure.

  • Cure and registration are judged together.

04 · A shifted drill removes annular margin on one side

Mechanical and laser vias face different geometry and heat effects.

Drilling turns design coordinates into hole-wall geometry. Tool wear, spindle runout, panel stacking and material movement all affect the result. Mechanical through-holes require diameter, position, roughness and smear checks, while laser microvias face different heat and stacking risks. Once a hole shifts and removes annular margin, additional plating cannot restore an inner-layer connection already cut away.

A dull drill tears resin and raises wall temperature, while wrong scale compensation shifts holes across the whole panel in one direction. If the drill revision disagrees with inner-layer data, a first panel may look acceptable while dense areas suffer breakout. Through-holes, blind vias and stacked microvias use different criteria; combining them into one diameter yield hides the most critical structures.

Before loading drill data, revision and panel coordinates are matched. Tools are managed by diameter and life, and the first panel is checked for position, annular ring, wall quality and smear. High-aspect-ratio and dense areas receive extra sections or imaging; systematic offset returns to scale and spindle rather than being left for plating. Material thickness, stack count or microvia design changes require new drilling parameters and acceptance methods.

  • Drill revision and panel coordinates must agree.

05 · Hole-wall copper must survive assembly and thermal cycling

Metallisation seeds conductivity before plating adds thickness.

Hole metallisation begins with desmear and activation to establish a conductive seed, followed by plating that carries assembly and thermal cycling. Bath balance, current distribution and aspect ratio create differences between the mouth and centre, so average copper does not represent the thinnest point. Backlight, sections, ductility and bath condition need to be interpreted within the same lot to establish continuity.

Poor activation leaves hidden voids, while current shielding makes the centre of a deep hole thinner than its mouth. Both may conduct during factory electrical test and open only after reflow or temperature cycling. Current density also differs between panel edge and centre, making convenient samples overly optimistic. Different aspect ratios cannot be solved merely by extending one plating time without upsetting surface copper.

Sampling covers panel edge, centre and high-aspect-ratio holes. Sections measure minimum copper and voids, with results linked to desmear, activation, current and bath run. Abnormal holes then undergo thermomechanical checks for assembly failure. Changes in panel current distribution, diameter or thickness require new rack and plating settings; acceptance rests on the least favourable hole rather than an attractive average.

  • Average copper cannot hide variation between mouth and centre.

06 · Impedance comes from geometry and dielectric, not trace width alone

Copper and dielectric thickness and etched sidewalls interact.

Controlled impedance arises from trace width, copper, dielectric thickness, dielectric properties, solder mask and reference plane; it is not decided by one line measurement. A coupon represents critical board nets only when stack, surrounding copper and etch conditions are comparable. Bandwidth and coupon position also matter, because one compliant impedance number cannot explain high-frequency loss or edge-panel variation.

Etching and plating near a panel edge may differ from the centre, and coupons placed only in favourable areas hide sidewall and copper changes on real traces. A coupon copied from an obsolete stack can produce a normal curve without physical correspondence to the current product. Roughness-related loss also grows with frequency, so compliant impedance does not establish the required high-speed insertion loss.

Coupons matching critical nets are placed at several panel positions. Stack and bandwidth are confirmed before measurement, and abnormal curves are resolved through sections of trace, copper and dielectric. Nets with unusual reference planes or mask openings receive representative structures rather than one universal coupon. A change in roughness, dielectric or frequency target prompts both impedance and insertion-loss checks instead of a width-only correction.

  • A coupon must represent the board structure.

07 · Solder mask and surface finish decide how pads are used

Aperture, cleanliness and shelf life affect assembly.

Solder-mask imaging, development and cure define pad openings, after which the metal finish determines solderability through storage. Uniform colour does not prove accurate apertures or cleanliness; adhesion, ionic residue, finish thickness and wetting observe different conditions. Packaging, humidity and thermal history also shape the assembly window, so finished boards are managed according to their actual surface system.

Chemical residue can remain invisible during electrical test and later create corrosion or leakage under power and humidity, while an aged finish encourages poor joints. A shifted mask opening covers usable pad area and is only temporarily disguised by extra solder. Surface finishes have different storage and heat-cycle limits; copying the shelf life of one system to another transfers avoidable risk to assembly.

Apertures and mask dams are inspected after development, followed by adhesion and representative film measurements after cure. Ionic residue after cleaning is checked against the intended assembly conditions. Each finish lot carries date, packaging and storage requirements, with solderability samples showing actual wetting. Rework or expired stock triggers the appropriate checks rather than relying on renewed appearance.

  • Solderability cannot be replaced by uniform colour.

08 · Electrical test finds opens and shorts, not every latent defect

Connectivity and long-term reliability occupy different time scales.

Flying probe or a fixture checks opens, shorts and isolation against the netlist, answering present connectivity rather than every latent reliability fault. Visual inspection, sections, ionic cleanliness and process anomalies remain relevant because thin hole copper or a resin void may conduct until assembly heat cycling. The finished trace code must correspond to the final customer data and manufacturing lot.

A wrong netlist makes the tester faithfully validate the wrong network, while a repaired board tested only at the patch may retain damage on adjacent traces. One overall pass rate does not show which structures concentrate faults; repeated opens, marginal resistance or visual defects in one area should lead back to process. Electrical acceptance also cannot replace thermal cycling or cleanliness because they address different failure times.

Before testing, the data checksum and programme revision are locked, and known defects confirm that the system detects opens and shorts. Repaired boards receive a full regression, with repair location, retest and appearance under one trace identity. Shipment combines netlist, electrical, visual and necessary section or reliability results. Any change in data, structure or repair extent reopens the affected checks instead of inheriting an old pass.

  • Release combines electrical, visual, section and process anomalies.

Sources and reading notes

Board identity, stack-up, material lot and process revision lead the assessment. Appearance, electrical test, microsection, impedance and reliability answer different questions; regional output or firm count describes scale rather than one board’s manufacturing history.

  • The cluster includes foil, laminate, PCB and compliant recovery, not all Zhanggong electronics.
  • Copper foil and PCB carry different manufacturing duties; upstream material figures are not finished-board figures.
  • Planned, under-construction, commissioned and statistical states remain separate; a plan is not stable current capacity.
  • High-frequency, HDI and ordinary multilayer boards differ in dielectric, microvia and impedance control and cannot share vague performance claims.

Related companies

These companies have a locally relevant industry role supported by public information. Order is not a ranking, inclusion does not imply authorization, partnership or endorsement, and Hello China does not participate in or guarantee transactions.

A company may request a free correction or removal through the formal channel if its record is inaccurate or it does not wish to be shown. Do not send business licences, authorization letters or other sensitive files through insecure channels.

  • Ganzhou Chaoyue Technology Co., Ltd. — The Zhanggong modernisation plan directly lists Chaoyue, while the high-tech-zone EIA classifies it in electronic-circuit manufacture. Together, those records bound Chaoyue to the stated processing stage.
  • Ganzhou Shenlian Circuit Co., Ltd. — The Zhanggong chain plan directly lists Shenlian and places it in the PCB chain under the high-tech zone. The same local record also fixes the manufacturing location in Zhanggong.
  • Jiangxi Yihao New Materials Co., Ltd. — Zhanggong material places Yihao in copper foil and electronic components, while listed-company disclosure provides legal identity and business direction.
  • Request a company-record correction or removal — Requests are reviewed by a person, handled promptly after verification, free of charge and not tied to commercial cooperation.

Sources

Use the original publishers to check dates, scope and definitions; public material is not a transaction guarantee.