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Chongqing Shapingba automotive power semiconductors

Automotive power devices switch large currents in charging, thermal management and traction. Beyond die size lie gate-oxide reliability, package parasitics, heat removal and long ageing. Shapingba spans wafers and packaging, yet automotive-test passage, stable production and vehicle nomination are three different states.

Formation and regional foundations

Xiyong’s eight-inch power-device base was upgraded before a twelve-inch wafer line and advanced power-packaging base entered production, building a local route from design through wafer and package. Vehicle demand pulls applications, while reliability platforms connect materials and process with automotive duty.

A power chip must switch efficiently and remain stable through temperature cycling, voltage transients and vibration. Wafer process forms the device, packaging connects electrical, thermal and mechanical paths, and vehicle qualification turns statistical reliability into production responsibility. All three are necessary.

Core geography: A semiconductor network around Xiyong and the Western Science City, linking power-device design, eight- and twelve-inch wafer manufacture, power packaging, reliability tests and automotive application

Five stations from power-device layout to vehicle controller

How wafer lot, package heat path and reliability data enter automotive supply

Device design turns duty into cell geometry, the fab manufactures by lot, and packaging builds external electrical and thermal interfaces. Reliability and application feedback both enter change control, so any process move returns to affected lots and qualification scope.

  • Device design and layout — Voltage, current and loss targets form cell and termination geometry.
  • Wafer manufacture and probe — Oxide, lithography, implant and metal create and screen die.
  • Power package and module — Bonding, interconnect, insulation and heat removal connect die to system.
  • Automotive reliability testing — Thermal, power cycling and bias tests expose long-term weakness.
  • Controller and vehicle introduction — Gate drive, cooling and fault strategy determine actual use.

01 · Define the switching duty

Voltage, current, frequency and short-circuit duty select the route.

Automotive power devices first face a vehicle load spectrum rather than one laboratory current rating. Traction inverters, onboard chargers and electric compressors impose different switching frequencies, junction-temperature swings, short-circuit demands and avalanche energy, so chips carrying the same current label may require different structures. A Shapingba team can judge the real margin of silicon or wide-bandgap devices only after placing the bus, motor, cooling circuit and control strategy in one duty map.

When a controller reports overcurrent during hot acceleration or a cold start, the first question is whether the device crossed its safe operating area, because a protection event alone does not indict the die. Topology, gate waveform, bus parasitics, coolant flow and software timing belong on one event sequence before comparison with estimated junction temperature and failure location. This separates a circuit transient, drive mismatch and an intrinsic device defect without turning one road incident into a vague conclusion.

Before the sample design is frozen, the vehicle team supplies voltage and current traces for traction, regenerative braking, fast charging and cold starts, enabling the device team to define combined junction-temperature, short-circuit and avalanche tests. Gate waveforms, bus ripple, coolant conditions and die lot travel with each result so that circuit-induced spikes are not mistaken for wafer defects. Device margin enters controller design only when calculated curves and measured traces agree at the harshest duty points.

  • Specification begins with circuit topology, not a package name.

02 · Layout and process shape the cell

Trench, termination and gate oxide balance voltage and loss.

Device layout arranges active cells, edge termination and metal interconnect within finite die area, while lithography alignment, implant profile and oxide quality jointly form the intended electric field, turning a drawn cell into an electric-field structure on the wafer. Higher cell density can reduce resistance while increasing gate charge and local heating, so layout density, gate charge and local heat cannot be optimised separately. If edge termination does not share a stable process with the active cells, efficient die area will not deliver a consistent blocking voltage.

Breakdown voltage develops a long tail near the wafer edge, which makes spatial distribution more informative than the average. Layout termination, local process uniformity and probe condition require separate checks, while the team checks whether anomalies follow a tool, mask position or probe contact. Correlating wafer maps, cross-sections and electrical distributions separates design boundaries from process uniformity, avoiding an unsupported whole-wafer change merely to remove an edge tail.

Layout review separates the cell field, termination and gate routing into manufacturable items, with threshold voltage, leakage and breakdown sampled independently on centre and edge dies. Implant dose, oxidation step, tool chamber and wafer position remain attached to every lot result, allowing a drift to return to a specific operation. The team expands wafer starts only after successive capability distributions cover the design window, rather than allowing one strong wafer to represent the route.

  • A design becomes manufacturable only within a stable wafer process.

03 · Eight and twelve inches have different rhythms

Tool generation, wafer area and thinning change manufacturing risk.

The eight-inch line carries mature power processes while twelve-inch wafers expand die count and use a new equipment set, and whole-wafer uniformity, warp, edge exclusion and automated handling become more sensitive on larger wafers, so the larger diameter changes whole-wafer control rather than die count alone. Historical eight-inch yield cannot stand in for the twelve-inch ramp, requiring fresh equipment windows for thin-wafer handling, backside metal and edge regions. Converting old-line yield directly into a new-line forecast would miss chamber differences, breakage risk and the real ramp rhythm.

When early-line yield varies with lot position and tool chamber, first ask whether defects stay with wafer position or a tool combination. Defect types should be tied to tool, wafer region and process sequence, then compare breakage, warp and backside steps along the same production sequence. Judging with stratified yield and repeated lots rather than one peak lot exposes limits introduced by diameter migration without treating one best lot as proof that the twelve-inch line is stable.

Platform transfer begins with a device structure that remains comparable on both wafer diameters, while thinning, backside metal and probing are assessed separately for warp and breakage. Pilot lots track critical parameters, yield and handling loss, retaining tool chamber and wafer position so an average cannot hide edge excursions. Capacity can ramp on engineering grounds only after several consecutive distributions converge and the observed failure mechanism remains unchanged.

  • A larger diameter does not allow every old process to move unchanged.

04 · Wafer probe removes unstable die

Probe bins carry electrical results into dicing and packaging.

Wafer probe measures threshold, conduction, leakage and breakdown before dicing, while test programme, contact resistance and temperature influence bins and wafer maps, and the bin result follows die coordinates into dicing and packaging. Tight limits reject good die while loose limits send weak die into packages, so probe limits cannot chase yield or pass every boundary die downstream. Without temperature and contact state, an anomaly shape on the wafer map may belong to the test fixture rather than fabrication.

If one wafer shows ring-shaped leakage or local contact anomalies, the reject count alone cannot establish a fabrication excursion. Engineers first observe whether the pattern moves after retest, probe-card replacement or temperature adjustment, then connect its location with equipment, mask position and neighbouring electrical parameters. A feature fixed to wafer coordinates is more likely process-related, whereas a pattern following test conditions points first to the probe or temperature control.

Wafer-screen limits are traced back from package and reliability failures, while the probe map preserves the coordinates and retest history of every die. Engineering lots add stress to termination areas, edge dies and statistical boundary samples, then compare the effects of temperature, probe contact and test order. The rule reduces system risk only when screened weaknesses correspond to a mechanism found in physical sections or downstream tests.

  • Poor test coverage moves expensive failures beyond module assembly.

05 · Package controls electrical and thermal exit

Attach, bonding, insulation and substrate form external interfaces.

Power packaging turns die capability into current and heat paths that a controller can use. Voids in the attach layer raise local thermal resistance, wire bonds or copper clips carry current cycling, and the insulated substrate must accommodate both thermal expansion and bus potential, leaving any mismatched interface able to fail before the die itself. Package evaluation therefore has to connect with the actual gate-drive loop, cooling boundary and switching waveform instead of relying on room-temperature static parameters.

If a module develops local heating or gate oscillation at high current, inspecting the die surface alone may miss an interconnect problem. Die loss, attach resistance, bus parasitics and cooler pressure need joint analysis, with drive edges, bus loop and cooler contact pressure reconstructed together. Combining thermal images, sections, double-pulse tests and thermal-resistance curves reveals interactions among the heat source, parasitics and material interfaces instead of hiding attach or layout defects by slowing the switch.

Controller voltage, current and cooling conditions set the package specification before switching and power cycling take place with the actual busbar, gate resistance and cold-plate boundary. Attach, interconnect, substrate and assembly lots remain linked to each sample, with thermography, waveforms and life results filed under the same identity. A package change benefits the complete unit only when local temperature rise, parasitic oscillation and cycling damage improve together.

  • A good die may lose margin in module interconnect.

06 · Automotive reliability must cover time

Thermal, bias and power cycling seek different long-term weaknesses.

Automotive reliability uses thermal cycling, high-temperature bias, humidity and power cycling to compress different years of vehicle stress into manageable test time. Gate oxide, edge termination, attach layers and metal interconnect respond through different mechanisms, so sample origin, preconditioning, load and failure criteria must be chosen around the intended weakness. One high-temperature pass or a certificate cannot replace this complementary programme of life assessment.

When parameters drift after stress without immediate failure, drift direction and sample clustering carry more meaning than a simple pass rate. Drift direction, lot clustering and later application margin need review, while asking whether the mechanism exists in vehicle temperature and load history. Combining life models, failure analysis and control samples connects electrical change to physical location, neither overlooking progressive ageing nor treating every small shift as imminent failure.

The reliability matrix assigns tests according to risks in gate oxide, termination, metal interconnect and package interfaces instead of forcing every sample through one ageing condition. Parameter checks, failure time and section location stay connected to wafer lot and sampling region, with boundary specimens drawn from different lots. Life inference gains a usable physical basis only when accelerated damage can explain electrothermal events seen in vehicle history.

  • One passed test cannot replace a complete stress matrix.

07 · Vehicle introduction requires system validation

Drive, cooling and fault strategy determine vehicle fitness.

Once a power device enters a controller, it forms a new electrothermal system with the gate drive, busbar, capacitor, cooler and software protection. Switching loss and safe operating area from the device report must pass through controller layout, short-circuit protection, thermal cycling and electromagnetic-compatibility work before becoming vehicle margin. Entry into a vehicle therefore depends on component coordination, and no isolated laboratory advantage covers road load.

If a controller that passed the bench derates or trips on a hot road, the difference often lies in cooling capacity, actual load spectrum or sensor response. Investigation aligns ambient temperature, coolant flow, software thresholds and device waveforms, marking the protection command relative to temperature rise and current transient. Shared logs and thermal points give the device, controller and vehicle teams one event to examine instead of separate presentations of their pass results.

Before vehicle trials, device, gate-drive, control and thermal specialists review the failure chain together, then schedule durability, boundary operation and fault injection. Control-software version, device lot, cooling state and bus logs are retained in synchrony so that a protection event can be reconstructed from its conditions. The controller proceeds to longer-mileage evaluation after all disciplines agree on safety margin and derating behaviour.

  • Supply approval is not a material certificate.

08 · Production changes need an impact boundary

Material, tool and programme changes trigger different requalification.

Volume production inevitably encounters material-lot changes, equipment maintenance, process adjustment and test-program revisions, and their effects on device life have different boundaries. Some variation remains in wafer parameters while another travels through attach or interconnect into long-term controller behaviour, so affected interfaces and failure modes must be mapped before adoption. Stable supply does not freeze the process, because it keeps old and new states, lot boundaries and customer approval identifiable.

When yield remains stable while a life distribution moves slowly, routine release charts may not show that risk is accumulating. The team compares material lots, equipment maintenance and program revisions on a timeline, then retests retained samples to determine whether drift is confined to a change boundary. Control charts show when movement began and reliability monitoring reveals its consequence, allowing gradual deviation to be intercepted without blaming ordinary variation.

When material, equipment, process or test software changes, the owner first identifies affected electrical parameters, interfaces and failure modes, then selects representative lots. Revalidation covers the most sensitive wafer locations and system duty points, with pre-change and post-change samples retained for physical comparison if an anomaly appears. The new state enters volume production after affected lots, release boundaries and the scope of customer approval are stated clearly.

  • Stable supply depends on traceable change, not no change.

Sources and reading notes

Set the route from voltage, current and switching duty for MOSFET, IGBT or silicon-carbide devices, then examine wafer process, die screening, package, thermal resistance and reliability. Automotive approval also requires change control and lot traceability and cannot be replaced by one laboratory pass.

  • A municipal report confirms CR Microelectronics Chongqing and its automotive power-device applications.
  • Science City material lists eight- and twelve-inch wafer lines, packaging lines and a laboratory.
  • The environmental list names CR Microelectronics and CR Runan as separate legal entities.
  • The EIA notice defines CR Runan packaging for power devices, IPM and IGBT modules.

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Sources

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