INDUSTRY CLUSTER · Electronics
Anxi semiconductor lighting
Substrate microdefects, post-package chromaticity drift and horticultural spectral mismatch occur at different stages. Review binds crystal lot, slice-grind-polish, chip electro-optics, die attach and wire bond, phosphor, thermal design, binning and ageing to the device lot.
Formation and regional foundations
Anxi places sapphire material and substrate, chips and packages, lighting applications, test and equipment near one another. Proximity shortens sample and logistics cycles, while substrate quality, device parameters and application approvals remain entity-, product- and lot-specific.
The Anxi review retains evidence through crystal, wafering, chip electro-optics, die attach and bond, phosphor and thermal design, binning and ageing application. The chain describes context; product, lot and tests carry device capability.
Core geography: The boundary covers the Anxi branch of Quanzhou Semiconductor High-Tech Park and evidenced production of sapphire crystal and substrates, LED chips, packaged devices, lighting and horticultural applications, and direct equipment. Generic lamp trade, assemblers without device manufacturing and photonics projects outside Anxi are excluded.
Semiconductor-lighting network from crystal to ageing
Six nodes across crystal, substrate, chip, package, bin and ageing
Adjacent stages do not make quality conclusions transferable.
- Crystal growth and orientation — Feed, run, thermal field, dopant and orientation enter the boule file.
- Slice, grind and polish — Gauge, warp, roughness and defect coordinates follow wafer.
- Epitaxy, chip and electro-optics — Wavelength, voltage, optical power and leakage form chip data.
- Die attach, wire bond and phosphor — Position, bonds, phosphor mix, dispense and cure bind to package lot.
- Thermal design and binning — Thermal resistance, flux, chromaticity, colour and spectrum are binned.
- Ageing and application validation — Climate, power, drive, spectral retention and failure bind to lot.
01 · Separate substrate, package and application issues
One efficacy number cannot cover three stages.
Substrate microdefects follow crystal run, orientation, slicing and polish; package colour drift adds die bin, phosphor ratio, dispense, cure and thermal path.
Horticultural mismatch also involves crop, stage, photoperiod, spectrum and spatial uniformity. Passing colour temperature does not prove a plant recipe.
Review fixes part number, lot, driver and use environment before sampling wafer, package or application.
02 · Crystal run starts the substrate record
Equal orientation can hide different defect density.
High-purity feed, seed, run, thermal field, growth or cooling jointly form the crystal. Boule identity retains head and tail.
Bubbles, cracks, dislocations and stress are sampled at defined positions. One middle coupon cannot represent a boule.
Sapphire serves other optical uses; lighting-chip substrate release cannot borrow generic window-material conclusions.
03 · Wafering turns boule into usable surface
Passing gauge does not prove a clean subsurface.
Slicing records tool, feed, coolant and orientation error; grinding and polishing record removal, pressure, slurry and pad.
Thickness variation, warp, bow, roughness, particles and scratches form a wafer map. Post-clean contamination is monitored separately.
Defect coordinates follow substrate into epitaxy and chip to separate inherited from new dark spots. Lot averages lose spatial links.
04 · Chip electro-optics must map to wafer position
Wavelength and optical power are not isolated values.
Epitaxy, uniformity, lithography, etch, metal contact and dicing jointly affect die. Key processes retain wafer identity.
Probe test records wavelength, forward voltage, optical power, leakage and electrostatic screening; bin boundaries track calibration.
Edge-centre distribution can reveal epitaxy or process drift. Final yield alone cannot show parameter movement.
05 · Packaging joins light, electricity and heat
Colour drift is rarely only a phosphor problem.
Die position, bondline, wire loop and pull affect connection and heat. Voids are related to thermal resistance and ageing.
Phosphor lot, ratio, settling, dispense and cure jointly set spectrum and chromaticity. One mix cannot exceed pot life.
Package cleanliness and electrostatic protection matter; contamination can cause leakage or interface ageing. Line environment stays with lot.
06 · Binning is part of product definition
Average flux cannot replace bin consistency.
Devices test flux, intensity, wavelength, chromaticity and colour under defined current, mode, temperature and geometry. Changed conditions move results.
Thermal resistance includes junction path, package and board heat. A lab heat sink does not represent an enclosed luminaire.
Bin labels and packing prevent colour mixing; rework is retested. Sparse sampling can still fail visual uniformity in luminaires.
07 · Ageing conditions must represent load
Burn time alone is not a life conclusion.
High-temperature life, humidity cycle, thermal shock and electrical stress follow device class, with current, junction estimate and failure criteria.
Flux retention, chromaticity shift, leakage and opens and shorts are counted separately. Still lit does not mean spectrum and colour remain in spec.
Horticultural use adds photon flux, spectral recipe, uniformity and crop response; general colour-temperature approval is not a substitute.
08 · Producer samples keep product boundaries
Substrate, package and application evidence do not transfer.
Jingan, Tiandian and Xindeco illustrate sapphire substrate, LED package and lighting application in Anxi. Co-location does not prove shared customers, parameters or capacity.
Thirty-five firms, RMB 28 billion and three Anxi samples come from city plan and park scope, not plant volume or device reliability.
Real coordination traces crystal run, substrate, wafer coordinate, package lot, bin, ageing sample and application feedback.
Sources and reading notes
MIIT, Quanzhou government, park plan and EIA establish national identity, boundary, producers and project status. Plan figures are not plant capacity, and application claims do not replace device approval.
- The MIIT list confirms the national formal name of Anxi’s semiconductor-lighting cluster.
- Quanzhou’s photonics plan records 35 photonics firms citywide.
- The same plan records total investment above RMB 28 billion for relevant projects.
- The plan identifies Jingan, Tiandian and Xindeco in the Anxi park.
Related companies
These companies have a locally relevant industry role supported by public information. Order is not a ranking, inclusion does not imply authorization, partnership or endorsement, and Hello China does not participate in or guarantee transactions.
A company may request a free correction or removal through the formal channel if its record is inaccurate or it does not wish to be shown. Do not send business licences, authorization letters or other sensitive files through insecure channels.
- Fujian Jingan Optoelectronics Co Ltd — Jingan manufactures sapphire crystal and substrates in the Anxi park; its role stops at material and substrate without inferring chip packaging.
- Fujian Tiandian Optoelectronics Co Ltd — Tiandian manufactures LED packages and optoelectronic devices in the Anxi park. Chip source, bin and package settings remain product-specific.
- Xiamen Xindeco Optoelectronics Technology Co Ltd — Xindeco carries lighting and optoelectronic application manufacturing in the Anxi park. Only park-evidenced roles are retained, excluding group business elsewhere.
- Request a company-record correction or removal — Requests are reviewed by a person, handled promptly after verification, free of charge and not tied to commercial cooperation.
Sources
Use the original publishers to check dates, scope and definitions; public material is not a transaction guarantee.
- 2024 national characteristic SME cluster list — Ministry of Industry and Information Technology of China
- Quanzhou photonics development plan — Quanzhou Semiconductor High-Tech Park Committee
- Anxi optoelectronics from substrate to application — Quanzhou Municipal People’s Government
- Anxi semiconductor industrial park EIA — Quanzhou Ecology and Environment Bureau
- Anxi semiconductor industrial park master plan — Quanzhou Municipal People’s Government
- 2024 work summary and park project progress — Quanzhou Semiconductor High-Tech Park Committee
- 2025 Quanzhou government work report — Quanzhou Municipal People’s Government
- Fujian electronic-component technology priorities — Fujian Department of Industry and Information Technology